This invention relates to a central processing unit (CPU) for an electronic data processing system and, more particularly to a CPU which places under program control the selection of the number of bits in an operand (operand width) used in a processor operation without requiring that information concerning the operand width be included in the operation code (op-code) of an instruction specifying the processor operation.
The op-code of an instruction is a group of binary digits (bits) that define a processor operation such as ADD, SUBTRACT, COMPLEMENT, etc. The set of processor operations formulated for a CPU depends on the processing it is intended to carry out. The total number of distinct operations which can be performed by the CPU determines its set of processor operations.
The number of bits which form the op-code (op-code field) is a function of the number of operations in the set. At least N bits are necessary to define 2.sup.N or less distinct operations. The CPU designer assigns a different bit combination (i.e., op-code) to each operation. The controller section of the CPU detects the bit combination at the proper time in a sequence and produces proper command signals to required destinations in the CPU to execute the specified operation.
In addition to specifying a processor operation, an instruction will normally also carry other information such as means for determining the address(es) of memory locations where operand(s) to be used in the processor operations are stored. In many instruction formats the number of bits required for the operand address(es) (address field) occupy most of the bit positions available in the instruction leaving only a limited number of bits to be allocated for the op-code field. When a CPU designer finds the bits allocated to the op-code field insufficient for a given set of processor operations he has, heretofore, had the choice of either accepting a smaller set of processor operations or lengthening the instruction.
A prior art technique for program selection of the operand width is to use designated bits in the op-code to specify the operand width. Where the op-code length is insufficient to define new codes, additional bits must be added to the op-code field. Thus separate op-codes would be used to define the same generic processor operation but for different operand widths (e.g., 4-BIT ADD, 8-BIT ADD). For example, if four different operand widths are to be used in all processor operations involving data, two bits in the op-code must be reserved for operand width specification. The effect of the additional bits in the op-code is to lengthen the instructions.
Long instructions are disadvantageous in small data processing systems where the memory capacity for storing instructions is limited. In addition, small systems have limited word sizes as well (as small as 4 bits in some systems where the CPU is in the form of a microprocessor), and a long instruction has the added disadvantage of requiring many memory references for retrieval and, thus, of slowing down CPU operation. However, from the standpoint of versatility, programming convenience, and operating efficienty, it is desirable to have software specification of the operand width. Therefore, a problem in designing a CPU for small data processing systems is that of being able to specify the operand width of processor operations while minimizing instruction length.